Department of Electrical Engineering, National Taipei University of Technology  
 2017/4/26 Wednesday Site Map Chinese version
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::: Mixed-mode IC Design 3 credit 3 hours
Verilog and VHDL, FPGA, ASIC, Combinational logic gates in CMOS, Timing issues in digital circuits, Comparator, Sample and Hold, Voltage reference, Translinear circuit, Data converter fundamentals, Nyquist-rate DAC, Nyquist-rate ADC, Oversampling converters, PLL, Noise and Mismatch.
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